Integrated circuits such as microprocessors typically send and receive information via digital signals transmitted on high-speed terminated buses. This places importance on the implementation of output driver circuitry having the drive strength to sent logic signals across the terminated buses without degradation of voltage swing levels. For example, in past situations where the output pad of the integrated circuit is coupled to a high-speed bus that has multiple connections to other devices, output drivers with insufficient current driving capability have suffered from diminished voltage swing levels. Basically, the open drain driver transistors lack the capacity to sink sufficient current at the output pad, which results in a logical low voltage (VOL) that deviates from the ideal, specified VOL level.
To alleviate this problem, various circuit designs have been proposed to provide current control for output drivers coupled to a high-speed bus. By way of example, U.S. Pat. Nos. 6,094,075; 6,009,487; 5,663,661; and 5,254,883 disclose techniques for controlling the transistor circuitry that controls bus current. What these techniques have in common is that they rely upon a current control value that is stored in a latch or register on the integrated circuit. The current control value is a calibrated digital value used to control the voltage swing level of the output drivers. The register or latch that stores the current control value is typically coupled to each of the output drivers of the chip.
The current control value is usually set in accordance with the particular application or type of bus to be driven (e.g., TTL, ECL, Rambus™, etc.). By way of example, the current control value that sets the voltage swing level for a Rambus™ open drain driver is typically determined by sampling two I/O bit cells. These two I/O slice voltage swings are compared to specific values and the control value is increased or decreased until the required voltage swing appears between these two I/O cells. The control logic then distributes the calibrated current control value among all the I/O cells on the integrated circuit.
However, there is a serious drawback of this approach. Sampling the voltage swings between only two bit cells and using this measurement to determine a single calibrated current control value for all the bit slices does not account for local abnormalities or process variations across the die. Transistor threshold voltage and other important transistor parameters often vary between each of the I/O bit slices. For instance, a normal Rambus application-specific cell (ASIC) has at least 26 I/O bit slices. This means that the transistor of the voltage comparator in the current control logic may not share the same transistor operating characteristics as the transistors in each of the I/O cells. Moreover, each Rambus ASIC cell is about 4000 microns wide, making variations across the die unavoidable.
Because of die process variations, the current control value distributed across the chip does not correctly calibrate every I/O driver cell. Indeed, many output drivers end up having voltage swing levels that are compromised due to local inaccuracies. Replicating the global current calibration logic and control logic in each of the I/O bit cells in order to calibrate each of the bits individually would, of course, be very costly in terms of silicon layout area and power consumption.
Therefore, what is needed is a new approach to the problem of current calibration to compensate for on-die process variations in output driver circuitry.